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Engineering · Electrical Engineering
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1) develop the state diagram for a mealy state machine that detects a sequence of three or more consecutive 1's in a string of bits coming through an input line

   write and verify a Verilog behavioral model of counter designed in problem 1

2) using manual method obtain the logic diagram of a three bit counter that count in the sequence     ( 0,2,4,6,0................)

write and verify the Verilog structural model of the counter described in problem 2

3) write and verify the Verilog behavioral model of a four bit counter that count in the sequence ( 0,1,2,3,4,5,6,7,8,9,0,1,2,..........)

PLEASE DO ALL QUESTIONS IN NEAT HANDWRITTING I AM POSTING THIS QUESTION 5TH TIME PLEASE MAKE SURE THAT YOUR ANSWERS ARE CORRECT PLEASE PLEASE DO ALL QUESTIONS

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