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Engineering · Electrical Engineering
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Consider a main memory built with SDRAM chips. Data are transferred in bursts as shown in figure 8.9, except that the burst length is 8. Assume that 32 bits of data are transferred in parallel. If a 400-MHz clock is used, how much time does it take to transfer:

(a). 32 bytes of data

(b) 64 bytes of data

What is the latency in each case?

Clock CAS Row Address Data Figure 8.9 A burst read of length 4 in an SDRAM. oles (we use 2 in the figure for simplicity) to activate the selected row. Then the column under of the CAS After a delay of one clock the of data hits placed on the data lines. The SDRAM automatically incremen paccess the next three sets of bits in the selected row, which are placed

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