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Engineering · Electrical Engineering
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In this question, you are asked to design a 4-bit register with both shift and parallel load features. The inputs of the register include a 2-bit control code X Y, a 4-bit input value I3 I2 I1 I0, and a clock signal. The outputs of the register are the 4 bits Q3 Q2 Q1 Q0 corresponding to the value stored in the register. The operations of the register is defined below:

XY Operation 0 0 Hold the current value stored (i.e Q3 Q2 Q1 Q0 are not changed) 0 1 Shift right (i.e new Q3-13, new Q2-Q3, new Q1 Q2, new Q0-Q1) 10 Shift left (i.e new Q3 2, new Q2 Q1, new Q1-Q0, new Q0-IO 1 1 Load new date (i.e new Q3-13, new Q2-12, new FIT, new Q0-IO

You are allow to use any number of D flip-flops, multiplexers of any size, decodes of any size, encoders of any size, AND gates, OR gates and NOT gates. (Notice that you may not need to use some of the devices listed above.) Please draw a circuit diagram to show your design. Please label your diagram clearly.

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